The invention relates generally to video signal processing and more particularly to a horizontal scaler for video decoding and method therefore.
Video signals originate from a variety of sources including TV tuners, digital video disc (DVD) players, video cassette recorders (VCRs), video cameras, etc. In many cases, the format of the video signal is improper for the display or processor to which the signal is routed. As such, horizontal and vertical scaling operations are performed on the video signal in order to adapt the video signal to the proper output configuration. In many cases, this adaptation or scaling of the video signal includes altering the data rate of the input video signal to match the desired clock rate of the output signal.
In many cases, scaling and aligning the data for display involves reducing the effective data rate of the signal. The lower data rate produced through scaling can force system designers to include large buffers to hold portions of data that arrive at a higher clock rate before they are able to be transmitted as an output signal at a lower clock rate. Depending on the level of scaling performed by the circuit, the size of these output buffers can be substantial. Large output buffers increase the die area of integrated circuits that perform these video decoding function, thus adding to overall system cost.
Therefore, a need exists for method and apparatus for scaling video signals while minimizing the amount of buffering required to accommodate the changes in data rate that occur between the received input video signal and the scaled output video signal.